With the rapid growth of wireless and portable consumer electronic devices, there have been increasing demands for new technological advancements with more and more functionalities being put into battery-operated electronic devices. This has resulted in increasing design and verification challenges for such low-power devices. There is also the corresponding problem in non-battery operated devices of excess heat production given the relatively large amounts of electric power typically used by current integrated circuits. Hence the need to reduce power is present not only in battery-operated devices but also in devices provided with mains electric current, due to the heat problem.
The pertinent challenges included minimizing leakage power dissipation, designing efficient packaging and cooling systems for high-power integrated circuit, and verifying functionalities of low-power or no power situations early in the design. Such power management issues become more critical in view of the continuous shrinking of integrated circuit (chip) device dimensions, that is the size of transistors, with each subsequent generation of transistors becoming smaller. Hence more and more power is being consumed in smaller and smaller devices resulting in significant heat issues. Addressing such power management issues has been identified by the industry as being critical in the integrated circuit design, especially for portable consumer electronic devices but not so limited.
Power consumption as well known has two components, dynamic and static power. Static power consumption is due to leakage current which is inherent in transistor devices. Dynamic power is a result of the switching activities of each transistor. Dynamic power consumption dominates total power consumption in integrated circuits (ICs). There are two types of multi-supply voltage known in the field. In the row-based type there are interleaved high and low supply voltage standard cell placement rows. In the region-based type, circuits are partitioned into voltage islands where each voltage island occupies a contiguous physical space and operates at a particular supply voltage and meets a particular performance requirement. This disclosure applies to both types, and other types, as long as there is a logical description of which cells or portions of an integrated circuit are contained in which power domains.
A power domain as described here has no physical restrictions in terms of the actual integrated circuit layout. More specifically, the dynamic electric power consumption P of an integrated circuit is measured by the equation P=k·f·C·V2, where k is the transistor switching speed, f is the IC clock frequency, C is the load capacitance, and V is the applied power (supply) voltage. Integrated circuit designs are typically partitioned into power domains. Each power domain has its own supply voltage level assigned so that all devices (transistors) in the domain are subject to the same input voltage. Various domains may have the same power levels, of course. Typical integrated circuits have two to ten or twenty domains, but this is not limiting. Each power domain may include one or more hierarchical modules, each of which includes several integrated circuit elements such as flip-flops (memory elements) and/or logic gates. Each flip-flop and logic gate typically includes one or more transistors (devices). Typically each individual power domain is assigned a voltage, from a fixed minimum to a fixed maximum. However the voltage of an IC can often be adjusted once it is placed on a circuit board.
Another relevant feature is delay or slack or signal propagation delay which is well known as a non-linear function of the input slew, the output capacitance (or impedance), and the supply voltage. Each flip-flop or logic gate in the design has its own slack value. Typically the slack value for any element of the design is the slack value of the longest path, which is the slowest signal path, through that element. The longest path going through the element is not necessarily the critical path. (We typically use the term critical path to define the slowest path of the entire design.) The slack values of all elements of a critical path are identical. This value is defined to be the slack of the critical path. It can be appreciated that each element has many signal paths, but as part of the IC design process, the longest path (slowest path) is routinely identified.
Therefore, there is a well known technical problem that high power consumption not only leads to shortened battery life for portable devices, not only computer devices but also cell phones, etc., and also causes on-chip thermal and reliability problems in general. Since as explained above power consumption is proportional to the square of the supply electrical voltage, reducing supply voltage significantly reduces power consumption. The above described power domain or multi-supply voltage (MSV) approach produces finer-grain power and performance tradeoffs. In this case performance refers to the slack or signal propagation delay. It is well known that there is the technical problem of tradeoffs between optimal power versus particular performance requirements, and/or optimal performance requirements versus particular power requirements. We are dealing with the tradeoff between power consumption and design performance. A user can ask what is the fastest design implementation under a power requirement or what is the lowest possible design implementation under a performance requirement. See for instance “Post-Placement Voltage Island Generation Under Performance Requirement”, Huaizhi WU et al., published by the IEEE, publication number 0-7803-9354-X/05, incorporated herein by reference in its entirety. See also “Timing-Constraint and Voltage-Island-Aware Voltage Assignment”, Huaizhi WU et al., published by the ACM, 2006, publication 1-59593-381-6/06/00007, also incorporated also herein by reference in its entirety.